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Pull requests: VHDL/Interfaces

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Pull requests list

Feature/wishbone Enhancement New feature or request Internal Mainly internal interface between components. Memory-Mapped SoC Bus Architecture
#38 opened Dec 11, 2025 by parhamsoltani Loading… v1.1
1
@parhamsoltani
10
Feature/avalon Enhancement New feature or request Internal Mainly internal interface between components. Memory-Mapped SoC Bus Architecture Streaming
#37 opened Dec 11, 2025 by parhamsoltani Loading… v1.1
2
@parhamsoltani
23
ProTip! Updated in the last three days: updated:>2025-12-17.