Metro: Add the capability for the sequencer FPGA to override the Versal boot mode

[isobering]

In Metro, strapping resistors on the Versal's MODE[3:0] pins configure the boot mode. Metro's strapping resistors are configured to select the QSPI32 (4-byte addressing) boot mode by default, which is required for Flash parts larger than 128Mib.

We also want Metro's sequencer FPGA to be able to override the boot mode strapping resistors in case we want to change the boot mode for bringup or debugging. To enable this, we wired the MODE bits to four sequencer FPGA pins through a pair of two-channel tristate buffers (U156 and U160). The sequencer FPGA also controls the buffers' active-low output enable signals, which is strapped high by default to disable the buffers. In normal operation, the buffer outputs are tristated, and the Versal strapping resistors select the boot mode, but if we want to override the strapping resistors, the sequencer FPGA can enable the buffers and assert a new MODE value before sequencing A0HP rails.

There are five signals involved in setting the boot mode:

FPGA1_TO_VERSAL_MODE_BUFFER_EN_L is the active-low buffer enable signal. A high level on FPGA1_TO_VERSAL_MODE_BUFFER_EN_L tristates the buffer outputs. A low level on FPGA1_TO_VERSAL_MODE_BUFFER_EN_L enables the buffers and allows the sequencer FPGA to set the boot mode.

• FPGA1_TO_VERSAL_MODE_BUFFER_EN_L is wired to FPGA1 ball J16 in bank 15.

FPGA1_TO_VERSAL_MODE_[3:0] are the four MODE bits. They are wired to four pins in FPGA1 Bank 36.

• MODE_3 is wired to ball B7 in Bank 36
• MODE_2 is wired to ball F6 in Bank 36
• MODE_1 is wired to ball E3 in Bank 36
• MODE_0 is wired to ball D2 in Bank 36

This comment in hardware-metro issue #48 describes the specific hardware implementation.