RISCV32 support for GNU

[kubeqz]

For the GNU toolchain, only the RISCV64 is supported now, can you please also add support for the RISCV32 ?

I can see there have been some efforts for that in the past #152 but that's not present on the master branch. What's the reason ? What's the current status ?

[fdesbiens]

Hi @kubeqz.

Thank you for reaching out.

I cannot comment on what Microsoft was doing back in 2021 and 2022. Unfortunately, whatever they were working on was never committed to the public GitHub repositories.

Bolstering our RISC-V support is an important goal for the project for 2026 and beyond. Supporting GCC is key to maximising adoption from our perspective as well.

The Eclipse Foundation is home to the OpenHW Foundation, which is working on verified open source RISC-V cores. You can access the System Verilog for those cores on GitHub. I am currently discussing with members of that community to work on ThreadX ports targeting the CV32E40P, CV-Wally and CVA6 cores. The Wally and CVA6 designs possess 32-bit and 64-bit configurations. Any ThreadX ports targeting those will rely on GCC.

I am also in touch with an OpenHW member interested in porting ThreadX to specific commercial RISC-V microcontrollers. Are there any in the market that would be of interest to you?

Ultimately, we are still a small team. If you have leads on individuals or companies who could be willing to assist us in porting, I am all ears...

[kubeqz]

Thanks for answering, I have mostly thought about some SiFive based microcontrollers like the one used in HiFive 1 https://www.sifive.com/boards/hifive1-rev-b or the Raspberry Pico 2 (with Hazard3 core).
Since there is already a port for IAR, I guess it's not that much different to gcc, or am I missing something ?