diff --git a/.DS_Store b/.DS_Store
new file mode 100644
index 0000000..0ac5640
Binary files /dev/null and b/.DS_Store differ
diff --git a/PixelFECInterface/dat/address_table.xml b/PixelFECInterface/dat/address_table.xml
index dbfe0f0..884ea8a 100644
--- a/PixelFECInterface/dat/address_table.xml
+++ b/PixelFECInterface/dat/address_table.xml
@@ -278,6 +278,10 @@
        <node id="TransTestM4C2"  mask="0x00000800" description="Trans Test M4 C2" />
        <node id="TTCLostLHC"     mask="0x00001000" description="Trans Test M4 C2" />
        <node id="RstTTCLostLHC"  mask="0x00002000" description="Trans Test M4 C2" />
+       <node id="PLLrst"         mask="0x00004000" description="PPL reset" />
+       <node id="IODelayInc"     mask="0x00030000" description="Increment  io delay by 1 unit" />
+       <node id="IODelayDec"     mask="0x00020000" description="Decrement  io delay by 1 unit" />
+       <node id="IODelay"        mask="0x0f800000" description="Read io delay setting" />
    </node>
 
    <node id="LHCCount" address="0x40000021" permission="r" mode="single"/>
diff --git a/PixelFECInterface/include/PixelPh1FECInterface.h b/PixelFECInterface/include/PixelPh1FECInterface.h
index 126cb3f..06d3361 100644
--- a/PixelFECInterface/include/PixelPh1FECInterface.h
+++ b/PixelFECInterface/include/PixelPh1FECInterface.h
@@ -20,13 +20,17 @@
 class PixelPh1FECInterface: public pos::PixelFECConfigInterface {
     
 public:
-  PixelPh1FECInterface(RegManager* const RegManagerPtr, const char* boardid);
-
-  bool hasclock();
-  bool clocklost();
-  void resetttc();
-  void resetclocklost();
-
+    PixelPh1FECInterface(RegManager* const RegManagerPtr, const char* boardid);
+    
+    bool hasclock();
+    bool clocklost();
+    void resetttc();
+    void resetclocklost();
+    void resetpll();
+    void ttcdelayinc();
+    void ttcdelaydec();
+    void readdelay();
+    
     int senddata(const int mfec, const int fecchannel);
     int injectrstroc(const int mfec, const int bitstate);
     int injecttrigger(const int mfec, const int bitstate);
@@ -43,8 +47,11 @@ class PixelPh1FECInterface: public pos::PixelFECConfigInterface {
     int getversion(const int mfec, unsigned long *data);
     int getversion(unsigned long *data);
     int getStatus(void);
+    
+    
+    
     unsigned getGeneral();
-
+    
     int writeCSregister(int mfec, int fecchannel, int cscommand);
     
     void mfecbusy(int mfec, int fecchannel, unsigned int *cs1,unsigned int *cs2);
@@ -205,21 +212,21 @@ class PixelPh1FECInterface: public pos::PixelFECConfigInterface {
                           unsigned char mask,
                           const bool buffermode = false);
     
-    void setAllDAC(const pos::PixelHdwAddress& theROC, 
+    void setAllDAC(const pos::PixelHdwAddress& theROC,
                    const std::vector<unsigned int>& dacs,
                    const bool buffermode = false);
     
     // from wolfram
     int testFiberEnable(const int mfec, const int enable);
     int testFiber(const int mfec, const int channel, int* rda, int * rck);
-
+    
     unsigned int flipByte(unsigned int input);
-	    
+    
 private:
     typedef uhal::ValWord<uint32_t> valword;
     typedef uhal::ValVector<uint32_t> valvec;
     RegManager * const pRegManager;
-
+    
     const std::string board_id;
     
     // ordering mfecs to match designations on vme card
@@ -243,7 +250,7 @@ class PixelPh1FECInterface: public pos::PixelFECConfigInterface {
     //int qbuflastport[9][3];
     
     int fecdebug;
-
+    
     std::vector<unsigned char> d25_trimloadtest;
 };
 
diff --git a/PixelFECInterface/src/common/PixelPh1FECInterface.cc b/PixelFECInterface/src/common/PixelPh1FECInterface.cc
index aed0b72..69c2f98 100644
--- a/PixelFECInterface/src/common/PixelPh1FECInterface.cc
+++ b/PixelFECInterface/src/common/PixelPh1FECInterface.cc
@@ -59,7 +59,7 @@ PixelPh1FECInterface::PixelPh1FECInterface(RegManager * const RegManagerPtr,
 
     pRegManager->WriteReg("ctrl.ttc_xpoint_A_out3", 0);
     usleep(100);
-    //resetttc();
+    resetttc();
     usleep(100);
     if (!hasclock() || clocklost()) {
       std::cerr << "hits go in wrong bx after clock lost until you reload firmware / power cycle\n";
@@ -91,6 +91,38 @@ void PixelPh1FECInterface::resetclocklost() {
   pRegManager->WriteReg("Board0.RstTTCLostLHC", 0);
 }
 
+//-----------------------------------------------------------------------
+void PixelPh1FECInterface::resetpll(){
+    
+    pRegManager->WriteReg("Board0.PLLrst", 1);
+    usleep(1000);
+    pRegManager->WriteReg("Board0.PLLrst", 0);
+}
+
+//-----------------------------------------------------------------------
+void PixelPh1FECInterface::ttcdelayinc(){
+
+    pRegManager->WriteReg("Board0.IODelayInc", 3);
+    resetttc();
+    readdelay();
+}
+
+//-----------------------------------------------------------------------
+void PixelPh1FECInterface::ttcdelaydec(){
+    
+    pRegManager->WriteReg("Board0.IODelayDec", 1);
+    resetttc();
+    readdelay();
+}
+
+//-----------------------------------------------------------------------
+void PixelPh1FECInterface::readdelay(){
+    valword value;
+    value = pRegManager->ReadReg("Board0.IODelay");
+    cout <<" The current io ttc delay setting is: " <<value.value()<<endl;
+}
+
+
 //-------------------------------------------------------------------------
 /* There are two versions of getversion() for both hal and CAEN (4 total)
  The form getversion(unsigned long *data) returns the integer 0..255
@@ -121,6 +153,7 @@ int PixelPh1FECInterface::getStatus(void) {
     if (PRINT) cout << "PixelPh1FECInterface: " <<"Get FEC status "<<value.value()<<endl;
     return value;
 }
+
 //--------------------------------------------------------------------------
 int PixelPh1FECInterface::getversion(const int mfec, unsigned long *data) {