[Feature Request] <Add support for ARM China STAR-MC3 CPU>

[cpussw01]

Is your feature request related to a problem? Please describe.
NO

Describe the solution you'd like
ARM China STAR-MC3 CPU is not supported by FreeRTOS kernel right now.
STAR-MC3 is new version of STAR-MC2 (Cortex-M52), there is No Architecture differences between them.
So, to add STAR-MC3 port, I just plan to copy CM52 port:

The changs may like :
refer: #1334
https://github.com/FreeRTOS/FreeRTOS-Kernel/tree/main/portable/GCC/ARM_CM52
https://github.com/FreeRTOS/FreeRTOS-Kernel/tree/main/portable/GCC/ARM_CM52_NTZ/
https://github.com/FreeRTOS/FreeRTOS-Kernel/tree/main/portable/IAR/ARM_CM52
https://github.com/FreeRTOS/FreeRTOS-Kernel/tree/main/portable/IAR/ARM_CM52
https://github.com/FreeRTOS/FreeRTOS-Kernel/tree/main/portable/IAR/ARM_CM52_NTZ/
Copy and Modify these files , to create corresponding STAR-MC3 port directory.

Wondering issues
I'm not sure , https://github.com/FreeRTOS/FreeRTOS-Kernel/tree/main/portable/ARMv8M directory should also be changed, just like CM52 port work do.
Before, this directory only list ARM_CM[23|33|52|55|85] port realted files.

I am asking for your advice. Will this STAR-MC3 port work be adviced? And, should the portable/ARMv8M directory also be changed?
Thank you!

[aggarg]

there is No Architecture differences between them.

If there is no difference, why can you not use Cortex-M52 port?

[cpussw01]

there is No Architecture differences between them.

If there is no difference, why can you not use Cortex-M52 port?

Hi aggarg, let me correct my description and explain my consideration:
STAR-MC3 has no main Architecture difference with Cortex-M52, but there are still some micro-architecture difference.

1 STAR-MC3 has no Cache/TCM, means both register map and functionality have some difference
As you can see, STAR-MC3 is supported by ARM CMSIS6 right now, https://github.com/ARM-software/CMSIS_6/blob/main/CMSIS/Core/Include/core_starmc3.h
These micro-architecture difference don't require changes of FreeRTOS-Kernel code and configurations.
But we need to choose FreeRTOS-Kernel CM52 port + CMSIS STAR-MC3 device, to make it correctly work.
This may make some users confused.

2 STAR-MC3 implement ACTLR.EXTEXCLALL bit, this makes Exclusive Access (LDREX/STREX) behavior different.
For STAR-MC3, ACLTL.EXTEXCLALL implementation make Exclusive Access behavior like Cortex-M23/33, different with Cortex-M52
This difference may have some impact on Kernel Semaphore/Mutex implementation and Synchronization mechanism (if LDREX/STREX is used)

[AhmedIsmail02]

Hello @cpussw01

With regard to point 2, I have a few clarifying questions:

1. Given that the Arm Cortex-M52 port layer does not currently make use of exclusive load/store instructions, do you expect the STAR-MC3 port layer implementation to differ in any way from the existing Cortex-M52 port?

2. The Cortex-M33 and Cortex-M52 ports (for example, port.c and portasm.c) are generated from the same common source set (see here). Since STAR-MC3 implements ACTLR.EXTEXCLALL with the same semantics as Cortex-M33, does this not imply that the existing port layer is already compatible with both cores that implement this bit and those that do not?

3. Have you already tested the existing Cortex-M52 FreeRTOS port on STAR-MC3 target? If so, were any functional issues observed that would require changes at the port layer?

Also, we could just add a note in the existing CM52 (or generic Armv8.1-M) port docs:

If using LDREX/STREX for synchronization with DMA/other masters, ensure the region is Shareable or (on cores that support it) enable EXTEXCLALL during platform init.